The present invention relates to semiconductor-on-insulator (SOI) structures, such as semiconductor on glass or glass ceramic, and methods for making same. In particular, the present invention relates to germanium on glass or glass-ceramic structures (GeOG), and more particularly germanium on expansion-matched glass or glass-ceramic substrates.
To date, the semiconductor material most commonly used in semiconductor-on-insulator structures has been silicon. Such structures have been referred to in the literature as silicon-on-insulator structures and the abbreviation “SOI” has been applied to such structures. Silicon-on-insulator technology is becoming increasingly important for high performance photovoltaic applications (e.g., solar cells), thin film transistor applications, and displays, such as, active matrix displays. Known silicon-on-insulator wafers consist of a thin layer of substantially single crystal silicon (generally 0.1-0.3 microns in thickness but, in some cases, as thick as 5 microns) on an insulating material.
For ease of presentation, the following discussion will at times be in terms of silicon-on-insulator structures. The references to this particular type of semiconductor-on-insulator structure are made to facilitate the explanation of the invention and are not intended to, and should not be interpreted as, limiting the invention's scope in any way. The SOI abbreviation is used herein to refer to semiconductor-on-insulator structures in general, including, but not limited to, both silicon-on-insulator and germanium-on-insulator structures. Similarly, the SOG abbreviation is used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on-glass (SiOG) and germanium-on-glass structures (GeOG). The SOG nomenclature is also intended to include semiconductor-on-glass-ceramic structures, including, but not limited to, silicon-on-glass-ceramic structures. The abbreviation SOI encompasses SOG structures.
The various ways of obtaining SOI structures include epitaxial growth of Si on lattice matched substrates. An alternative process includes the bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SiO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.1 to 0.3 micron layer of single crystal silicon. Further methods include ion-implantation methods in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
The former two methods have not resulted in satisfactory structures in terms of cost and/or bond strength and durability. The latter method involving hydrogen ion implantation has received some attention and has been considered advantageous over the former methods because the implantation energies required are less than 50% of that of oxygen ion implants and the dosage required is two orders of magnitude lower.
Exfoliation by the hydrogen ion implantation method typically consists of the following steps. A thermal oxide layer is grown on a single crystal silicon wafer. Hydrogen ions are then implanted into this wafer to generate subsurface flaws. The implantation energy determines the depth at which the flaws are generated and the dosage determines flaw density. This wafer is then placed into contact with another silicon wafer (the support substrate) at room temperature to form a tentative bond. The wafers are then heat-treated to about 600 degrees C. to cause growth of the subsurface flaws for use in separating a thin layer of silicon from the Si wafer. The resulting assembly is then heated to a temperature above 1,000 degrees C. to fully bond the Si film with SiO2 underlayer to the support substrate, i.e., the unimplanted Si wafer. This process thus forms an SOI structure with a thin film of silicon bonded to another silicon wafer with an oxide insulator layer in between.
Cost is an important consideration for commercial applications of SOI structures. To date, a major part of the cost of the above-described method and structure has been the cost of the silicon wafer which supports the oxide layer, topped by the Si thin film, i.e., a major part of the cost has been the support substrate. Although the use of quartz as a support substrate has been mentioned in various patents (see U.S. Pat. Nos. 6,140,209 6,211,041, 6,309,950, 6,323,108, 6,335,231, and 6,391,740), quartz is itself a relatively expensive material. In discussing support substrates, some of the above references have mentioned quartz glass, glass, and glass-ceramics. Other support substrate materials listed in these references include diamond, sapphire, silicon carbide, silicon nitride, ceramics, metals, and plastics.
U.S. Pat. No. 5,374,564 discloses a process to obtain a single crystal silicon film on a substrate using a thermal process. A semiconductor material wafer having a planar face is subject to the following steps: (i) implantation by bombardment of a face of the wafer by means of ions creating a layer of gaseous micro-bubbles defining a lower region constituting the mass of the substrate and an upper region constituting the thin film; (ii) contacting the planar face of the wafer with a stiffener constituted by at least one rigid material layer; and (iii) a third stage of heat treating the assembly of the wafer and the stiffener at a temperature above that at which the ion bombardment was carried out and sufficient to create a pressure effect in the micro-bubbles and a separation between the thin film and the mass of the substrate. Due to the high temperature steps, this process does not work with lower cost glass or glass-ceramic substrates.
U.S. Patent Application No.: 2004/0229444 discloses a process for producing a SOG structure. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) cooling the structure to a common temperature to facilitate separation of the glass substrate and a thin layer of silicon from the silicon wafer. The SOI formation technique disclosed in U.S. Patent Application No.: 2004/0229444 has been shown to result in a relatively thin semiconductor layer (e.g., about 1-5 um) bonded to a glass substrate.
While this semiconductor thickness is sufficient for some if not most applications, and is an improvement over such over bulk semiconductor materials which typically exhibit thicknesses of at least 200 microns thick, these silicon or silicon-based alloys/oxide glass or an oxide glass-ceramic based SOI structures may not provide a satisfactory layer semiconductor thickness for other applications; e.g., MOS transistors, optical detectors and other optoelectronic devices, and high performance solar cells/photovoltaic devices.
Recently, structures for achieving thinner semiconductor layer SOI structures have been described in US Pat. Apps. 2005/0093100 and 2005/0042842, and U.S. Pat. No. 6,759,712; in particular methods of making devices based on germanium-on-insulator, also known as GOI, are disclosed. The semiconductor conducting films disclosed in the aforementioned GOI applications generally have thicknesses of less than 200 nm (0.2 microns). As disclosed therein, germanium is effective in thin film, high performance/high quantum efficiency applications/devices as a result of germanium's higher carrier (hole and electron) mobility and optical absorption when compared to those of silicon. In addition to having high electron and hole mobilities, germanium has other advantages such as lower contact resistance and lower dopant activation temperatures than those required by silicon, thus facilitating the formation of shallow junctions.
While the “insulator” described in references these studies is generally a buried insulator layer, typically an oxide or nitride, within a semiconducting material (Ge, Si, GaAs, SiC . . . ), glass is disclosed as a possible, non-semiconducting material, substrate. One problem associated with the use of glass as a substrate material when bonded to Ge is the potential thermal expansion mismatch between the Ge film and the substrate to which it is bonded; this phenomenon is particularly problematic in the case of Ge film on a silica glass. Significant expansion mismatches would lead to high film stresses and probable crazing or delamination.
Despite the above described benefits of thin-film GeOI devices, the above mismatch problem when utilizing glass as the insulator/substrate, is still prevalent and has not been addressed. As such, there is a need for GeOI, particularly GeOG devices which comprise a glass insulator/substrate that does not exhibit the aforementioned expansion mismatch problem; i.e., a GeOG device in which the substrate possesses thermal expansion characteristics that are compatible with those CTE characteristics of the Ge semiconducting film.